# 

#  Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
#
#
# 
#  Copyright Exar 2010. Copyright (c) 2002-2010 Neterion, Inc.
#  All right Reserved.
# 
#  FileName :    vxge.conf
#
#  Description:  Neterion X3100 configuration file

# Uncomment the line(s) below if you'd like to override default values

#------------------------------------------
# Jumbo frame support
#	This option will require at least 8MB of extra physical memory allocated
#	in the kernel.
#	Set to maximum MTU to be supported by X3100 interface
#------------------------------------------
#default_mtu = 9000;

#------------------------------------------
# MSI-X interrupts
#	0 - Disable
#	1 - Enable
#------------------------------------------
#msix_enable = 1;

#------------------------------------------
# Large Send Offload
#	0 - Disable
#	1 - Enable
#------------------------------------------
#lso_enable = 1;

#------------------------------------------
# Maximum Number of vpaths
#	Set to maximum number of vpaths to be used by each function(device)
#	SPARC: max_config_vpath = 6;
#	x86  : max_config_vpath = 8;
#------------------------------------------
#max_config_vpath = 8;

#------------------------------------------
# Receive Traffic Hash
#	0 - Disable
#	1 - Enable
#------------------------------------------
#rth_enable = 1;

#------------------------------------------
# Tx Steering
#	0 - Disable
#	1 - Steering based on TCP/UDP ports
#------------------------------------------
#tx_steering_type = 0;

#------------------------------------------
# Flow control
# For both, flow_control_gen (Tx) and flow_control_rcv (Rx)
#	0 - Disable
#	1 - Enable
#------------------------------------------
#flow_control_gen = 1;
#flow_control_rcv = 1;

#------------------------------------------
#stats_refresh_time = 1;
#isr_polling_cnt = 0;
#rts_mac_en = 0;

#------------------------------------------
# F/W Upgrade
#	0 - Disable
#	1 - Enable
#fw_upgrade = 1;

#------------------------------------------
# Function Mode
#       Change PCI function mode.
#       0  - SF1_VP17 (1 function with 17 VPATHs)
#       1  - MF8_VP2  (8 functions with 2 VPATHs per function)
#       8  - MF2_VP8  (2 functions, 8 Paths/Function)
#       9  - MF4_VP4  (4 Functions, 4 Paths/Function)
#	0xFF - Default, No change
#------------------------------------------
#func_mode = 0xFF;

# Port Mode
#	Change the default dual port mode
#	0 - Default
#	1 - Hardware Link Aggregation
#	2 - Active Passive
#	3 - Single Port
#	4 - Dual Port
#	5 - Disable adapter port management
#	0xFF - Default, No change
#------------------------------------------
#port_mode = 0xFF;

# port_failure:
#	Change the behavior on failure
#	0 - No failover
#	    If the port goes down all traffic destined to this port
#	    will be dropped
#	1 - Failover only
#	    If a port fails, move to the active port.
#	    If the previously failed port recovers don't switch back.
#	    However, if the current port now fails the traffic will
#	    move to the active port.
#	2 - Failover and fail back.
#	    If a port (or active port) fails switch to the other port
#	    that is up.
#	    If the previous port recovers revert back to the original port.
#	0xFF - Default, No change
#------------------------------------------
#port_failure = 0xFF;

#------------------------------------------
# Maximum Number of Device function to be configured in MF mode
#	MIN - 1 and MAX - 8
#	0xFF - Default, No change
#------------------------------------------
#max_config_dev = 0xFF;

#------------------------------------------
# FMA support
#------------------------------------------
#fm-capable = 0xF;

#------------------------------------------
# FIFO Configuration
#------------------------------------------
#max_fifo_cnt = 1;
#fifo_length = 512;
#fifo_max_frags = 64;
#fifo_no_snoop_bits = 0;
#fifo_dma_lowat = 64;

#------------------------------------------
# TTI Configuration
#------------------------------------------
#tti_intr_enable = 1;
#tti_btimer_val = 250;
#tti_timer_ac_en = 1;
#tti_timer_ci_en = 1;
#tti_timer_ri_en = 0;
#tti_rtimer_event_sf = 0;
#tti_util_sel = 17;
#tti_ltimer_val = 3677;
#tti_rtimer_val = 1838;
#tti_txfrm_cnt_enable = 1;
#tti_txd_cnt_en = 0;
#tti_urange_a = 5;
#tti_urange_b = 15;
#tti_urange_c = 40;
#tti_uec_a = 5;
#tti_uec_b = 40;
#tti_uec_c = 60;
#tti_uec_d = 100;

#------------------------------------------
# Ring Configuration
#------------------------------------------
#ring_length = 512;
#ring_max_frm_len = 1522;
#ring_backoff_interval_us = 64;
#ring_indicate_max_pkts = 256;
#ring_no_snoop_bits = 0;
#ring_dma_lowat = 128;
#rx_timer_val = 4;
#rx_pkt_burst = 2;

#------------------------------------------
# Rx Buffer Pool Parameters
#
# Suggested values:
# If VXGE_RX_BUFFER_RECYCLE is defined
# rx_buffer_total_per_rxd      : 127 * 6   =   762
# rx_buffer_post_hiwat_per_rxd : 127 * 4   =   508
# If VXGE_RX_BUFFER_RECYCLE is not defined
# rx_buffer_total_per_rxd      : 127 * 128 = 16256
# rx_buffer_post_hiwat_per_rxd : 127 * 64  =  8128
#------------------------------------------
#rx_buffer_total_per_rxd = 762;
#rx_buffer_post_hiwat_per_rxd = 508;

#------------------------------------------
# RTI Configuration
#------------------------------------------
#rti_intr_enable = 1;
#rti_btimer_val = 250;
#rti_timer_ac_en = 0;
#rti_timer_ci_en = 0;
#rti_timer_ri_en = 0;
#rti_rtimer_event_sf = 0;
#rti_util_sel = 18;
#rti_urange_a = 10;
#rti_urange_b = 30;
#rti_urange_c = 50;
#rti_uec_a = 1;
#rti_uec_b = 5;
#rti_uec_c = 10;
#rti_uec_d = 15;
#rti_rtimer_val = 0;
#rti_ltimer_val = 1000;
#rti_txfrm_cnt_enable = 1;
#rti_txd_cnt_en = 0;

#------------------------------------------
# * Tracing for ULD, trace_mask flags to Enable tracing
#	XGE_DEBUG_INIT		0x00000001
#	XGE_DEBUG_TX		0x00000002
#	XGE_DEBUG_RX		0x00000004
#	XGE_DEBUG_MEM		0x00000008
#	XGE_DEBUG_LOCK		0x00000010
#	XGE_DEBUG_SEM		0x00000020
#	XGE_DEBUG_ENTRYEXIT	0x00000040
#	XGE_DEBUG_INTR		0x00000080
#------------------------------------------
#trace_mask = 0x0;
#####################################################################
# TRACE SECTION:
# Possible values for MODULE, TRACE and ERR masks:
#####################################################################
#
#define VXGE_COMPONENT_HAL_DEVICE                       0x00000001
#define VXGE_COMPONENT_HAL_DEVICE_IRQ                   0x00000002
#define VXGE_COMPONENT_HAL_VPATH                        0x00000004
#define VXGE_COMPONENT_HAL_VPATH_IRQ                    0x00000008
#define VXGE_COMPONENT_HAL_CONFIG                       0x00000010
#define VXGE_COMPONENT_HAL_MM                           0x00000020
#define VXGE_COMPONENT_HAL_POOL                         0x00000040
#define VXGE_COMPONENT_HAL_QUEUE                        0x00000080
#define VXGE_COMPONENT_HAL_BITMAP                       0x00000100
#define VXGE_COMPONENT_HAL_CHANNEL                      0x00000200
#define VXGE_COMPONENT_HAL_FIFO                         0x00000400
#define VXGE_COMPONENT_HAL_RING                         0x00000800
#define VXGE_COMPONENT_HAL_DMQ                          0x00001000
#define VXGE_COMPONENT_HAL_UMQ                          0x00002000
#define VXGE_COMPONENT_HAL_SQ                           0x00004000
#define VXGE_COMPONENT_HAL_SRQ                          0x00008000
#define VXGE_COMPONENT_HAL_CQRQ                         0x00010000
#define VXGE_COMPONENT_HAL_NCE                          0x00020000
#define VXGE_COMPONENT_HAL_STAG                         0x00040000
#define VXGE_COMPONENT_HAL_TCP                          0x00080000
#define VXGE_COMPONENT_HAL_LRO                          0x00100000
#define VXGE_COMPONENT_HAL_SPDM                         0x00200000
#define VXGE_COMPONENT_HAL_SESSION                      0x00400000
#define VXGE_COMPONENT_HAL_STATS                        0x00800000
#define VXGE_COMPONENT_HAL_MRPCIM                       0x01000000
#define VXGE_COMPONENT_HAL_MRPCIM_IRQ                   0x02000000
#define VXGE_COMPONENT_HAL_SRPCIM                       0x04000000
#define VXGE_COMPONENT_HAL_SRPCIM_IRQ                   0x08000000
#define VXGE_COMPONENT_HAL_DRIVER                       0x10000000

#define VXGE_COMPONENT_OSDEP                            0x20000000
#define VXGE_COMPONENT_LL                               0x40000000
#define VXGE_COMPONENT_ALL                              0xffffffff
#debug_module_mask = 0x40000000;
# debug_level -  VXGE_NONE = 0, VXGE_ERR = 1, VXGE_INFO = 2 VXGE_TRACE = 4.
#debug_module_level = 0;