ELF>4@@    @ @$$$$$ $$ $0$@$$''''((HHHIIIILLNQQQQY Y Y@Y[ [[@[O\\\^``````ccyyyyyyyyy y y0y0yyy$y$y<AA  0@ @            @     `  ! A B Ё Ђ    @       @    @ @$$$$$ $$ $0$@$$''''(((((HHHIIIILLNQQQQY Y Y@Y[ [[@[O\\\^```````ccyyyyyyyyy y0y0yyy$y$y<AA 00@@              @     `  ! A B Ё Ђ   @       @ $$$$$ $$ $0'''(((HIIIILQ\\\^_yyyyyy0y0AA@@ 0 0          @    `  ! A B Ё Ђ    @      @    @ @$$$$$ $@$$$ $0$'''((((HHHIIIILLQXXXX\\\^^_```````ccyyyyy y0y0yyyyyyy$y$y<AA@@ 0 0            @    `  ! A B Ё Ђ      @        @ ,inv,br_misp_retired.all_branchesbr_inst_retired.all_brancheslongest_lat_cache.miss,PAPI_l3_tcmlongest_lat_cache.reference,PAPI_l3_tcacpu_clk_unhalted.ref_p,cpu_clk_thread_unhalted.ref_xclkinst_retired.any_p,PAPI_tot_inscpu_clk_unhalted.thread_p,PAPI_tot_cyccmaskedgeumaskPAPI_anythrcpu_clk_unhalted.refcpu_clk_unhalted.thread,PAPI_tot_cycinstr_retired.any,PAPI_tot_insedge,inv,umask,cmask,anythrIntel Arch PerfMon v%d on Family %d Model %din_txcpin_txmsr_offcoreCore Performance CountersR15R14R13R12R11R10RSPRBPRDIRSIRDXRCXRBXRAXRIPl2_lines_in.alll2_trans.l1d_wbl2_trans.all_pfitlb.itlb_flushidq.ms_dsb_uopsidq.mite_cyclesl1d.replacementl2_rqsts.all_pfl2_rqsts.pf_hituops_issued.anyld_blocks.no_srmem_trans_retired.load_latency,mem_trans_retired.precise_storeLatency ValueData Source EncodingData Linear AddressIA32_PERF_GLOBAL_STATUSR9R8*RFLAGSsq_misc.split_lockl2_lines_out.dirty_alll2_lines_out.pf_dirtyl2_lines_out.pf_cleanl2_lines_out.demand_dirtyl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdmem_load_uops_misc_retired.llc_missmem_load_uops_llc_hit_retired.xsnp_nonemem_load_uops_llc_hit_retired.xsnp_hitmmem_load_uops_llc_hit_retired.xsnp_hitmem_load_uops_llc_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.llc_hitmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uop_retired.all_storesmem_uop_retired.all_loadsmem_uop_retired.split_storesmem_uop_retired.split_loadsmem_uop_retired.lock_loadsmem_uop_retired.stlb_miss_storesmem_uop_retired.stlb_miss_loadsmem_trans_retired.precise_storemem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputfp_assist.x87_inputfp_assist.x87_outputbr_misp_retired.takenbr_misp_retired.not_takenbr_misp_retired.all_branchesbr_misp_retired.near_callbr_misp_retired.conditionalbr_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branchesbr_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.smcmachine_clears.memory_orderinguops_retired.retire_slotsuops_retired.stall_cyclesuops_retired.active_cyclesuops_retired.allother_assists.sse_to_avxother_assists.avx_to_sseother_assists.avx_storeother_assists.itlb_miss_retiredinst_retired.x87inst_retired.prec_distl1d_blocks.bank_conflict_cyclestlb_flush.stlb_anytlb_flush.dtlb_threadoff_core_response_1off_core_response_0agu_bypass_cancel.countoffcore_requests_buffer.sq_fulluops_dispatched.coreuops_dispatched.stall_cyclesuops_dispatched.threadoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_data_rddsb_fill.all_canceldsb_fill.exceed_dsb_linesdsb_fill.other_canceldsb2mite_switches.penalty_cyclesdsb2mite_switches.countresource_stalls.otherresource_stalls.mxcsrresource_stalls.fcswresource_stalls.robresource_stalls.sbresource_stalls.rsresource_stalls.lbresource_stalls.anyuops_dispatched_port.port_5uops_dispatched_port.port_4uops_dispatched_port.port_3uops_dispatched_port.port_3_stauops_dispatched_port.port_3_lduops_dispatched_port.port_2uops_dispatched_port.port_2_stauops_dispatched_port.port_2_lduops_dispatched_port.port_1uops_dispatched_port.port_0idq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.all_condbr_misp_exec.taken_indirect_near_callbr_misp_exec.taken_direct_near_callbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jmp_non_call_retbr_misp_exec.taken_condbr_misp_exec.nontaken_condbr_inst_exec.all_branchesbr_inst_exec.all_condbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_return_nearbr_inst_exec.taken_indirect_jmp_non_call_retbr_inst_exec.taken_direct_jmpbr_inst_exec.taken_condbr_inst_exec.nontaken_condild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.miss_causes_a_walkicache.missesidq.mite_all_uopsidq.all_mite_cyclesidq.all_mite_uopsidq.all_dsb_cyclesidq.all_dsb_uopsidq.ms_cyclesidq.ms_uopsidq.ms_mite_cyclesidq.ms_mite_uopsidq.ms_dsb_activationsidq.ms_dsb_cyclesidq.dsb_cyclesidq.dsb_uopsidq.mite_uopsidq.emptylock_cycles.cache_lock_durationlock_cycles.split_lock_uc_lock_durationoffcore_requests_outstanding.all_data_rd_cyclesoffcore_requests_outstanding.all_data_rdoffcore_requests_outstanding.demand_rfo_cyclesoffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.demand_data_rd_cyclesoffcore_requests_outstanding.demand_data_rdrs_events.empty_cyclescpl_cycles.ring123cpl_cycles.ring0_transitioncpl_cycles.ring0resource_stalls2.ooo_rsrcresource_stalls2.bob_fullresource_stalls2.all_prf_controlresource_stalls2.all_fl_emptypartial_rat_stalls.mul_single_uoppartial_rat_stalls.slow_lea_windowpartial_rat_stalls.flags_merge_uop_cyclespartial_rat_stalls.flags_merge_uopl1d.all_m_replacementl1d.evictionl1d.allocated_in_mhw_pre_req.dl1_missload_hit_pre.hw_pfload_hit_pre.sw_pfdtlb_store_misses.stlb_hitdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.miss_causes_a_walkl1d_pend_miss.pending_cyclesl1d_pend_miss.occurrencesl1d_pend_miss.pendingl2_l1d_wb_rqsts.hit_ml2_l1d_wb_rqsts.hit_el2_store_lock_rqsts.alll2_store_lock_rqsts.hit_ml2_store_lock_rqsts.hit_el2_store_lock_rqsts.missl2_rqsts.pf_missl2_rqsts.all_code_rdl2_rqsts.code_rd_missl2_rqsts.code_rd_hitl2_rqsts.all_rfol2_rqsts.rfo_missl2_rqsts.rfo_hitsl2_rqsts.all_demand_data_rdl2_rqsts.demand_data_rd_hitinsts_written_to_iq.instsarith.fpu_divarith.fpu_div_activesimd_fp_256.packed_doublesimd_fp_256.packed_singlefp_comp_ops_exe.sse_scalar_doublefp_comp_ops_exe.sse_packed singlefp_comp_ops_exe.sse_fp_scalar_singlefp_comp_ops_exe.sse_fp_packed_doublefp_comp_ops_exe.x87uops_issued.core_stall_cyclesuops_issued.stall_cyclesint_misc.rat_stall_cyclesint_misc.recovery_cycles_countint_misc.recovery_cyclesdtlb_load_misses.stlb_hitdtlb_load_misses.walk_durationdtlb_load_misses.walk_completeddtlb_load_misses.miss_causes_a_walkld_blocks_partial.all_sta_blockld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.all_blockld_blocks.store_forwardld_blocks.data_unknownSee Appendix A of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2" Order Number: 253669-038US, April 2011l2_lines_in.alll2_trans.l1d_wbl2_trans.all_pfitlb.itlb_flushidq.ms_dsb_uopsidq.mite_cyclesl1d.replacementl2_rqsts.all_pfl2_rqsts.pf_hituops_issued.anyld_blocks.no_srsq_misc.split_lockl2_lines_out.dirty_alll2_lines_out.pf_dirtyl2_lines_out.pf_cleanl2_lines_out.demand_dirtyl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdmem_load_uops_misc_retired.llc_missmem_load_uops_llc_hit_retired.xsnp_nonemem_load_uops_llc_hit_retired.xsnp_hitmmem_load_uops_llc_hit_retired.xsnp_hitmem_load_uops_llc_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uops_retired.all_storesmem_uops_retired.all_loadsmem_uops_retired.split_storesmem_uops_retired.split_loadsmem_uops_retired.lock_loadsmem_uops_retired.stlb_miss_storesmem_uops_retired.stlb_miss_loadsmem_trans_retired.precise_storemem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputfp_assist.x87_inputfp_assist.x87_outputbr_misp_retired.takenbr_misp_retired.not_takenbr_misp_retired.all_branchesbr_misp_retired.near_callbr_misp_retired.conditionalbr_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branchesbr_inst_retired.near_call_r3br_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.smcmachine_clears.memory_orderinguops_retired.retire_slotsuops_retired.core_stall_cyclesuops_retired.total_cyclesuops_retired.stall_cyclesuops_retired.allother_assists.sse_to_avxother_assists.avx_to_sseother_assists.avx_storeother_assists.itlb_miss_retiredinst_retired.x87inst_retired.prec_distl1d_blocks.bank_conflict_cyclestlb_flush.stlb_anytlb_flush.dtlb_threadoffcore_response_1offcore_response_0agu_bypass_cancel.countoffcore_requests_buffer.sq_fulluops_dispatched.coreuops_dispatched.stall_cyclesuops_dispatched.threadoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_code_rdoffcore_requests.demand_data_rddsb_fill.all_canceldsb_fill.exceed_dsb_linesdsb_fill.other_canceldsb2mite_switches.penalty_cyclesdsb2mite_switches.countresource_stalls.ooo_rsrcresource_stalls.robresource_stalls.mem_rsresource_stalls.lb_sbresource_stalls.sbresource_stalls.rsresource_stalls.lbresource_stalls.anyuops_dispatched_port.port_5_coreuops_dispatched_port.port_5uops_dispatched_port.port_4_coreuops_dispatched_port.port_4uops_dispatched_port.port_3_coreuops_dispatched_port.port_3uops_dispatched_port.port_2_coreuops_dispatched_port.port_2uops_dispatched_port.port_1_coreuops_dispatched_port.port_1uops_dispatched_port.port_0_coreuops_dispatched_port.port_0idq_uops_not_delivered.cycles_fe_was_okidq_uops_not_delivered.cycles_ge_1_uop_deliv.coreidq_uops_not_delivered.cycles_le_3_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_0_uops_deliv.coreidq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.all_direct_near_callbr_misp_exec.all_indirect_jump_non_call_retbr_misp_exec.all_conditionalbr_misp_exec.taken_indirect_near_callbr_misp_exec.taken_direct_near_callbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jump_non_call_retbr_misp_exec.taken_conditionalbr_misp_exec.nontaken_conditionalbr_inst_exec.all_branchesbr_inst_exec.all_direct_near_callbr_inst_exec.all_indirect_near_returnbr_inst_exec.all_indirect_jump_non_call_retbr_inst_exec.all_direct_jmpbr_inst_exec.all_conditionalbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_indirect_near_returnbr_inst_exec.taken_indirect_jump_non_call_retbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_conditionalbr_inst_exec.nontaken_conditionalild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.miss_causes_a_walkicache.missesidq.mite_all_uopsidq.all_mite_cycles_any_uopsidq.all_mite_cycles_4_uopsidq.all_dsb_cycles_any_uopsidq.all_dsb_cycles_4_uopsidq.ms_cyclesidq.ms_uopsidq.ms_mite_uopsidq.ms_dsb_occuridq.ms_dsb_cyclesidq.dsb_cyclesidq.dsb_uopsidq.mite_uopsidq.emptylock_cycles.cache_lock_durationlock_cycles.split_lock_uc_lock_durationoffcore_requests_outstanding.cycles_with_data_rdoffcore_requests_outstanding.all_data_rdoffcore_requests_outstanding.cycles_with_demand_rfooffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.demand_code_rdoffcore_requests_outstanding.cycles_with_demand_data_rdoffcore_requests_outstanding.demand_data_rdrs_events.empty_cyclescpl_cycles.ring123cpl_cycles.ring0_transcpl_cycles.ring0resource_stalls2.ooo_rsrcresource_stalls2.bob_fullresource_stalls2.all_prf_controlresource_stalls2.all_fl_emptypartial_rat_stalls.mul_single_uoppartial_rat_stalls.slow_lea_windowpartial_rat_stalls.flags_merge_uop_cyclespartial_rat_stalls.flags_merge_uopl1d.all_m_replacementl1d.evictionl1d.allocated_in_mhw_pre_req.dl1_missload_hit_pre.hw_pfload_hit_pre.sw_pfdtlb_store_misses.stlb_hitdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.miss_causes_a_walkl1d_pend_miss.occurencesl1d_pend_miss.pending_cyclesl1d_pend_miss.pendingl2_l1d_wb_rqsts.alll2_l1d_wb_rqsts.hit_ml2_l1d_wb_rqsts.hit_el2_l1d_wb_rqsts.hit_sl2_l1d_wb_rqsts.missl2_store_lock_rqsts.alll2_store_lock_rqsts.hit_ml2_store_lock_rqsts.hit_el2_store_lock_rqsts.missl2_rqsts.pf_missl2_rqsts.all_code_rdl2_rqsts.code_rd_missl2_rqsts.code_rd_hitl2_rqsts.all_rfol2_rqsts.rfo_missl2_rqsts.rfo_hitl2_rqsts.all_demand_data_rdl2_rqsts.demand_data_rd_hitinsts_written_to_iq.instsarith.fpu_divarith.fpu_div_activesimd_fp_256.packed_doublesimd_fp_256.packed_singlefp_comp_ops_exe.sse_scalar_doublefp_comp_ops_exe.sse_packed_singlefp_comp_ops_exe.sse_scalar_singlefp_comp_ops_exe.sse_packed_doublefp_comp_ops_exe.x87uops_issued.core_stall_cyclesuops_issued.stall_cyclesint_misc.rat_stall_cyclesint_misc.recovery_stalls_countint_misc.recovery_cyclesdtlb_load_misses.stlb_hitdtlb_load_misses.walk_durationdtlb_load_misses.walk_completeddtlb_load_misses.miss_causes_a_walkld_blocks_partial.all_sta_blockld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.all_blockld_blocks.store_forwardld_blocks.data_unknownSee Appendix A of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2" Order Number: 253669-038US, October 2011l2_lines_in.alll2_trans.l1d_wbitlb.itlb_flushidq.mite_cyclesl1d.replacementuops_issued.anyl2_lines_out.dirty_alll2_lines_out.demand_dirtyl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdmem_load_uops_llc_miss_retired.local_drammem_load_uops_llc_hit_retired.xsnp_nonemem_load_uops_llc_hit_retired.xsnp_hitmmem_load_uops_llc_hit_retired.xsnp_hitmem_load_uops_llc_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.llc_hitmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uops_retired.all_storesmem_uops_retired.all_loadsmem_uops_retired.split_storesmem_uops_retired.split_loadsmem_uops_retired.lock_loadsmem_uops_retired.stlb_miss_storesmem_uops_retired.stlb_miss_loadsmem_trans_retired.precise_storemem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputbr_misp_retired.near_takenbr_misp_retired.all_branchesbr_misp_retired.conditionalbr_inst_retired.near_call_r3br_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branchesbr_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.memory_orderinguops_retired.retire_slotsuops_retired.total_cyclesuops_retired.allother_assists.sse_to_avxother_assists.avx_to_sseother_assists.avx_storeinst_retired.prec_distoffcore_response_1offcore_response_0uops_executed.coreuops_executed.threadoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_code_rdoffcore_requests.demand_data_rddsb_fill.exceed_dsb_linesdsb2mite_switches.penalty_cyclesdsb2mite_switches.countresource_stalls.robresource_stalls.sbresource_stalls.rsresource_stalls.anyuops_dispatched_port.port_3_coreuops_dispatched_port.port_2_coreuops_dispatched_port.port_3uops_dispatched_port.port_2uops_dispatched_port.port_5_coreuops_dispatched_port.port_4_coreuops_dispatched_port.port_1_coreuops_dispatched_port.port_0_coreuops_dispatched_port.port_5uops_dispatched_port.port_4uops_dispatched_port.port_1uops_dispatched_port.port_0idq_uops_not_delivered.cycles_le_3_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_0_uops_deliv.coreidq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.all_indirect_jump_non_call_retbr_misp_exec.all_conditionalbr_misp_exec.taken_indirect_near_callbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jump_non_call_retbr_misp_exec.taken_conditionalbr_misp_exec.nontaken_conditionalbr_inst_exec.all_branchesbr_inst_exec.all_direct_near_callbr_inst_exec.all_indirect_near_returnbr_inst_exec.all_indirect_jump_non_call_retbr_inst_exec.all_direct_jmpbr_inst_exec.all_conditionalbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_indirect_near_returnbr_inst_exec.taken_indirect_jump_non_call_retbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_conditionalbr_inst_exec.nontaken_conditionalild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.miss_causes_a_walkicache.missesidq.ms_cyclesidq.ms_uopsidq.dsb_cyclesidq.dsb_uopsidq.mite_uopsidq.emptytlb_access.load_stlb_hitrs_events.empty_cyclescpl_cycles.ring0_transcpl_cycles.ring123cpl_cycles.ring0load_hit_pre.sw_pfdtlb_store_misses.stlb_hitdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.miss_causes_a_walkl1d_pend_miss.occurencesl2_l1d_wb_rqsts.hit_ml2_l1d_wb_rqsts.hit_el2_l1d_wb_rqsts.missl2_store_lock_rqsts.alll2_store_lock_rqsts.hit_ml2_store_lock_rqsts.missl2_rqsts.all_code_rdl2_rqsts.all_rfol2_rqsts.all_demand_data_rdl2_rqsts.code_rd_missl2_rqsts.code_rd_hitl2_rqsts.rfo_missl2_rqsts.rfo_hitl2_rqsts.demand_data_rd_hitarith.fpu_divarith.fpu_div_activeuops_issued.stall_cyclesdtlb_load_misses.demand_ld_walk_durationdtlb_load_misses.demand_ld_walk_completeddtlb_load_misses.demand_ld_miss_causes_a_walkld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.store_forwardSee Appendix A of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2" Order Number: 253669-038US, October 2011l2_lines_in.alll2_trans.l1d_wbl2_trans.all_pfitlb.itlb_flushidq.mite_cyclesidq.ms_dsb_uopsl1d.replacementl2_rqsts.all_pfl2_rqsts.pf_hituops_issued.anyld_blocks.no_sruops_executed.cycles_ge_4_uops_execuops_executed.cycles_ge_3_uops_execuops_executed.cycles_ge_2_uops_execuops_executed.cycles_ge_1_uop_execl2_lines_out.dirty_alll2_lines_out.pf_dirtyl2_lines_out.pf_cleanl2_lines_out.demand_dirtyl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdbaclears.anymem_load_uops_llc_miss_retired.remote_fwdmem_load_uops_llc_miss_retired.remote_hitmmem_load_uops_llc_miss_retired.remote_drammem_load_uops_llc_miss_retired.local_drammem_load_uops_llc_hit_retired.xsnp_nonemem_load_uops_llc_hit_retired.xsnp_hitmmem_load_uops_llc_hit_retired.xsnp_hitmem_load_uops_llc_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.llc_missmem_load_uops_retired.l2_missmem_load_uops_retired.l1_missmem_load_uops_retired.llc_hitmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uops_retired.all_storesmem_uops_retired.all_loadsmem_uops_retired.split_storesmem_uops_retired.split_loadsmem_uops_retired.lock_loadsmem_uops_retired.stlb_miss_storesmem_uops_retired.stlb_miss_loadsmem_trans_retired.precise_storemem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputfp_assist.x87_inputfp_assist.x87_outputbr_misp_retired.near_takenbr_misp_retired.all_branchesbr_misp_retired.conditionalbr_inst_retired.near_call_r3br_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branchesbr_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.smcmachine_clears.memory_orderingmachine_clears.countuops_retired.core_stall_cyclesuops_retired.total_cyclesuops_retired.stall_cyclesuops_retired.retire_slotsuops_retired.allother_assists.any_wb_assistother_assists.sse_to_avxother_assists.avx_to_sseother_assists.avx_storeinst_retired.prec_disttlb_flush.stlb_anytlb_flush.dtlb_threadoffcore_response_1offcore_response_0uops_executed.stall_cyclesuops_executed.coreuops_executed.threadoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_code_rdoffcore_requests.demand_data_rddsb_fill.exceed_dsb_linesdsb2mite_switches.penalty_cyclesdsb2mite_switches.countlsd.cycles_4_uopslsd.cycles_activelsd.uopscycle_activity.stalls_l1d_pendingcycle_activity.stalls_ldm_pendingcycle_activity.stalls_l2_pendingcycle_activity.cycles_no_executecycle_activity.cycles_ldm_pendingcycle_activity.cycles_l1d_pendingcycle_activity.cycles_l2_pendingresource_stalls.robresource_stalls.sbresource_stalls.rsresource_stalls.anyuops_dispatched_port.port_3_coreuops_dispatched_port.port_2_coreuops_dispatched_port.port_3uops_dispatched_port.port_2uops_dispatched_port.port_5_coreuops_dispatched_port.port_4_coreuops_dispatched_port.port_1_coreuops_dispatched_port.port_0_coreuops_dispatched_port.port_5uops_dispatched_port.port_4uops_dispatched_port.port_1uops_dispatched_port.port_0idq_uops_not_delivered.cycles_fe_was_okidq_uops_not_delivered.cycles_le_3_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_0_uops_deliv.coreidq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.all_indirect_jump_non_call_retbr_misp_exec.all_conditionalbr_misp_exec.taken_indirect_near_callbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jump_non_call_retbr_misp_exec.taken_conditionalbr_misp_exec.nontaken_conditionalbr_inst_exec.all_branchesbr_inst_exec.all_direct_near_callbr_inst_exec.all_indirect_near_returnbr_inst_exec.all_indirect_jump_non_call_retbr_inst_exec.all_direct_jmpbr_inst_exec.all_conditionalbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_indirect_near_returnbr_inst_exec.taken_indirect_jump_non_call_retbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_conditionalbr_inst_exec.nontaken_conditionalild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.miss_causes_a_walkicache.ifetch_stallicache.missesidq.mite_all_uopsidq.all_mite_cycles_any_uopsidq.all_mite_cycles_4_uopsidq.all_dsb_cycles_any_uopsidq.all_dsb_cycles_4_uopsidq.ms_dsb_occuridq.ms_dsb_cyclesidq.dsb_cyclesidq.ms_cyclesidq.ms_uopsidq.ms_mite_uopsidq.dsb_uopsidq.mite_uopsidq.emptylock_cycles.cache_lock_durationlock_cycles.split_lock_uc_lock_durationoffcore_requests_outstanding.cycles_with_demand_rfooffcore_requests_outstanding.cycles_with_data_rdoffcore_requests_outstanding.cycles_with_demand_data_rdoffcore_requests_outstanding.all_data_rdoffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.demand_code_rdoffcore_requests_outstanding.demand_data_rddtlb_load_misses.stlb_hitrs_events.empty_end rs_events.empty_cyclescpl_cycles.ring0_transcpl_cycles.ring123cpl_cycles.ring0move_elimination.simd_eliminatedmove_elimination.int_eliminatedmove_elimination.simd_not_eliminatedmove_elimination.int_not_eliminatedload_hit_pre.hw_pfload_hit_pre.sw_pfdtlb_store_misses.stlb_hitdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.miss_causes_a_walkl1d_pend_miss.occurencesl1d_pend_miss.pending_cyclesl1d_pend_miss.pendingl2_l1d_wb_rqsts.alll2_l1d_wb_rqsts.hit_ml2_l1d_wb_rqsts.hit_el2_l1d_wb_rqsts.missl2_store_lock_rqsts.alll2_store_lock_rqsts.hit_ml2_store_lock_rqsts.missl2_rqsts.all_code_rdl2_rqsts.all_rfol2_rqsts.all_demand_data_rdl2_rqsts.pf_missl2_rqsts.code_rd_missl2_rqsts.code_rd_hitl2_rqsts.rfo_missl2_rqsts.rfo_hitl2_rqsts.demand_data_rd_hitarith.fpu_divarith.fpu_div_activesimd_fp_256.packed_doublesimd_fp_256.packed_singlefp_comp_ops_exe.sse_scalar_doublefp_comp_ops_exe.sse_packed_singlefp_comp_ops_exe.sse_scalar_singlefp_comp_ops_exe.sse_packed_doublefp_comp_ops_exe.x87uops_issued.single_muluops_issued.slow_leauops_issued.flags_mergeuops_issued.core_stall_cyclesuops_issued.stall_cyclesint_misc.recovery_stalls_countint_misc.recovery_cyclesdtlb_load_misses.large_page_walk_completeddtlb_load_misses.walk_durationdtlb_load_misses.walk_completeddtlb_load_misses.miss_causes_a_walkld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.store_forwardSee Chapter 19.3 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide" Order Number: 325384-046US, March 2013invld_lat_thresholdedge,inv,umask,cmask,anythr,smpl_nrecsPEBSrecitemsbitmapindexsupportednitems,anythrcmaskedgesmpl_nrecsin_txcpld_lat_thresholdin_txffffffUHffffffUHffffffUH=ueH%H=ueH%HH=H3H3ffffffffUHHH}HuSATAUAVAWHLLH5IHILHI+Ht>L-L;uIIItL{IIHI+Hu3 IIHA_A^A]A\[ÐffffffUHffffffUHffffffffUHHffffffffUHffffffffUHffffffffUHHffffffffUHHffffffffUHHffffffffUHHffffffffUHffffffffUHffffffUHHffffffffUH fffffffUHSHeH%HtEH}} rkEH}E騀t4EHHEHH HE H}E} H}H}CH}: H='uH=(t HH H HH HH=H HdDDH3H3HH5H3H[ÐUHHH}G ЃHGHHHHHHHHH=H5fffffffUHHH}HuHHt,tHvuH#=Hz H#=HzfffffffUHHH}+;rH3HÐffffffUHHH}SATAUAVHLM33ۅ~>L-I}Iu HcL I;|IHA^A]A\[ffffffUHH0H}HuHUHMLELMSATAUAVAWHDLDELMA+;r HH3EtTAH5H}HHE3Hx teH%HudAtAtAtH 3 D+D`L#-LhXHMH3 HA_A^A]A\[ÐffffffUHHH}SATAUAVAWHLH3M3M3H3LMtdA>uHA^ H}IvIvH}AF HcL HK HL IIH3LMuIHǍIIHA_A^A]A\[ÐffffffUHHH}HuSATAUAVLLH3H5H5HǐLIuHI#HI I3tIHIH3AH It IH HHǏHA^A]A\[UHHH}HHHHHHHHH5H=ffffffUHH0H}HuHUHMLELMSATAUAVAWHHtHhLDEILmH HHMHEHH HEHM=u'IHtHIH#HHH;9Mt EEHhLMt|Ew)IEEIEEtEL#=L}@H=HhHt&IEEIEEtEL#=L}WHxHhH33lExEtEL#=L}EDžtL{ HH5HuHI H=ID}#HH5Hu&HUHH%MHHH HHH5Hu&HUHH%MHHH HHH5HuHC H H=D}mHH5HtH=Ht@oeH%HHUHH%MHHH HH(ttA;AtHMHH HAtHMHH HAtHMHH HHMHH @HH 3HMHHMHUHHPHMHUHHHP3 LmHHA_A^A]A\[ÐffffffUHHH}HuSATL=u`IHt:HIH#HHH;t H3HH3M38IHIIHIIA\[fUHHH}HGHHHGwx3Ʌ~%LHcHt3AI;~ffffffffUHHH}SATAUAVHLH3E3~9L%I<$ItIAD;| IcHHH#HA^A]A\[ÐUHHH}SATAULE3~:HH;ItHAD;|IcHHH3A]A\[fffffffUHHH}HuHUSATAUAVAWH LLU5E3~DEHE3EtH{5IcHDLcHAD;|HU3HuH3AL}MtQME3H3AׅtEEtIIcHDLcËHuHUH3AL}MuEuH3Ic3H~UMEL5EEAt"IvHHH5IEE;|HU3HuH3AHE}Ht]MEE3H3Aׅt#EEtHHuHH5AAHuHUH3AHE}HuAIcHH A_A^A]A\[fUHHH}SATAUAVAWHL翎HHǎHL;H(HǍHHHHH03I IE3HLHHHH(HuH3IQL HH!(A  IIH H3IH3IIAMD;uH(HǍH(=HH(LPL}HE3IA HI$HHHHHuH3IsL (HHH HHA IHH H3HH3HIIAMD;"HH H(H ؿHHǏHH3HǏH3HHǍH~\L0H IE3HLt&M}A$ IHIHIAMD;|~wHPLmIdžIE3H(Lt9I}AH3H A$IH IHIAMD;|HA_A^A]A\[UHHH}SATAUAVAWH HH HH#L%L#H HHHE HHU=vlI IE3ItAA }HEIHHEHMHt}H3IH3IAMD;|=vcII3Mt;}LIIHELt}H3IH3IM;|H A_A^A]A\[fffffffUHSATHHǎHHHǐHHH H# HH@H H#LL tH HtHH3H3%IA\[ffffffffUH쿏H3HǏH3H%HffffffffUHHffffffffUHHH}SATAULH=HH=ItWIH|3LH5IH5IIIH=HsL-A]A\[ffffffUHHH}SATAUAVAWHLLmIH3ILMEfAt;Av AAHIHHML%(A AHIHHML%HIHHUI#IFH;sL"IL"HUIFHH+H I^IIILM;HA_A^A]A\[fffffffUHHH}HH fffffffUHHH};ffffffffUHHH} ;;#ffffffUHSH=u?HHHHHHHH[ffffffUHHH}u H u HH3HffffffUHu t 0H=փ%Hc$tH=H=H%HHH%H?HatH=H=H%HHH%Hw?HtH=H=H%HHH%Hw?HtH=H=H%HHH%Hw?H H%HHH%H?HH%HHH%H?HH%HHH%H?HEH%HHH%H??HH=fffffffUHH=fffffffUHHH}HHH=ffUHHffUHHH}Huu3fUHHH}HuHU;=}HcHkHH HH@H3UHHH}SATAUAVHDIcH3LEn3E~&MH=H5=IIA;~IHA^A]A\[UHHH}SATHDtJH=u1H=H=uAJHH=HHH3HA\[UHHH}Su `[ÐUHHH}SATAUAVAWLM3HH E3=~9M3J|1IH tIAD;=| IcHkDdIH#A_A^A]A\[UHHH}SATAULLI\HII H A]A\[UHH0H}HuHUHMLELMSATAUAVAWHDLLELM HuHuH>tI3D;r Au7AuiHuAII֋ELM HEHuAII֋ELMH!uuAII֋ELMHHA_A^A]A\[ÐUHHH}SATAUHH E3=~9M3J|!HH tIAD;-| IcHkHH3A]A\[fUHHH}53҅~'H H@88t H;| HcHkHH3UHH0H}HuHUHMLELMSATAUAVAWH(DHHUMEMHLMHtAAFIuH3PuAHHUMEMH؅HEL8EIEHC HEHH5HuBIGHH#H}HH H IGHH Ht H%IGHH5Hu3AIGHH#H}HH!H IGH(EEA;:MIFtIOHMHMHAGAFtIGH IGAFtIGH IGAFtIGH IGAFt1IGHH IOAFtHIOAFtAuIGHH IGA?t <A?IGHEH}&LMAFtwH3HEfANfH3HHEvGM3IH5H t I(A;rHcHk(ID H#HMHAHEIG<3E3D;v2HIHH tI(AE;r 3IH3HMHH(A_A^A]A\[fUHHH}HHH= ffUHHH}SATAUAVAWLH3H3H3LMAMAvugEeI}AIEM}MtA?IwI?IwE$IuAIuIHIHH IIH3LMnHA_A^A]A\[fUHHH}SHߋHvuH{Ht HH[ÐUHHH}HGH HHLHHwH;r H3HHHGHO HUHHH}HuHUSHHCHC HKH;r H3HHH HHLHHHHC HKH;uHCHH;r H3HHHCHHC [ÐUHHH}HuDHHHH#3H33D;vHHHtHtH A;rUHHH}HHt7533;v"HHHu;r HH#H UHHH}HuSATAUAVAWH(LeH%HHHcIHMHc0HEILx HX(ML;s\LeIIHEHt1I/t$HcHk(I~IHU/I u܋MlL;rILx(H(A_A^A]A\[UHHH}HuHUS3DN3E3E3;~HL_HKHk(It I+t HHHN{$tAtH;~HAE;~HHQ(Et(0 HHA8HGHA8G0HGHA8[fffffffUHHH}HuHHt H#=HxffffffffUHH0H}HuHUHMLELMSATAUAVAWH8DEIH HHpHxHH HEHMHHEHHH#ȃ=uHtHHHH;9DžpHUHEHBEtHxEmE3L{ HH5H u D}HH5Hu$HEH%MHHH HEHH5Hu$HEH%MHHH HEHH5HuHI H=D}kHH5HtH=Ht>XeH%HHEH%MHHH HEH(AE;AtHEH HEAtHEH HEAtEHEH @HEH(3HMHHpHxHHPHMHUHHHPHMHH 3 H8A_A^A]A\[ffffffUHHH}SATAUAVAWH H}H3HEHH0HEH0HH}H3H3ҹLMEeAD$HMH H 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