ELF>@@@  @`   @$!$A$0$P$$$$$B$"$D$$$'$$?$'PHHHIIIIII I@I`ILLOQTTTTTT T@XXXX\\\]]]]]^^````````ccyyyyy y0y0y0yyyyyyy$y$y< @`AA @ @  !"$( @         @      @Ȁ  @ɀ `  ! A B Ё Ђ      @       @ @`  @$!$"$$$'$0$?$A$B$D$P$$$$$$'PHHIIIIII I@I`ILLOQTTTTTT T@XXXX\\\]]]]]^^``````ccyyyyyyyyyyy y$y$y0y0y0y< @`AA @@  !"$(ABDH  @         @     @Ȁ  @ɀ `  ! A B Ё Ђ      @         @ @`    @$!$A$0$P$$$$$B$"$D$$$'$$?$'P<HHHIIIIII I@I`ILLOQTTTTTT T@XXXX\\\]]]]]^^````````ccyyyyyyyyyyy y$y$y0y0y0y< @`AA @ @  !"$  @         @           @Ȁ  @ɀ `  ! " A B Ё Ђ      @       @ @`     @$!$A$0$P$$$$$B$"$D$$$'$$?$'P<<<HHHHHIIIIII I@I`ILLOQTTTTTT T@XXXX\\\]]]]]^^`````````ccyyyyyyyyyyy y$y$y0y0y0y< @`AA @ @  !"$(  @         @           * <   @Ȁ  @ɀ `  ! " A B Ё Ђ      @       @,inv,br_misp_retired.all_branchesbr_inst_retired.all_brancheslongest_lat_cache.miss,PAPI_l3_tcmlongest_lat_cache.reference,PAPI_l3_tcacpu_clk_unhalted.ref_p,cpu_clk_thread_unhalted.ref_xclkinst_retired.any_p,PAPI_tot_inscpu_clk_unhalted.thread_p,PAPI_tot_cyccmaskedgeumaskPAPI_anythrcpu_clk_unhalted.refcpu_clk_unhalted.thread,PAPI_tot_cycinstr_retired.any,PAPI_tot_insedge,inv,umask,cmask,anythrIntel Arch PerfMon v%d on Family %d Model %din_txcpin_txmsr_offcoreCore Performance CountersR15R14R13R12R11R10RSPRBPRDIRSIRDXRCXRBXRAXRIPl2_lines_in.alll2_trans.l1d_wbl2_trans.all_pfitlb.itlb_flushidq.mite_cyclesidq.ms_switchesidq.ms_dsb_uopsl1d.replacementept.walk_cyclesl2_rqsts.all_pfuops_issued.anyld_blocks.no_srhle_retired.aborted,rtm_retired.abortedmem_trans_retired.load_latency,mem_uops_retired.stlb_miss_loads,mem_uops_retired.stlb_miss_stores,mem_uops_retired.lock_loads,mem_uops_retired.split_loads,mem_uops_retired.split_stores,mem_uops_retired.all_loads,mem_uops_retired.all_stores,mem_load_uops_retired.l1_hit,mem_load_uops_retired.l2_hit,mem_load_uops_retired.l3_hit,mem_load_uops_retired.l1_miss,mem_load_uops_retired.l2_miss,mem_load_uops_retired.l3_miss,mem_load_uops_retired.hit_lfb,mem_load_uops_l3_hit_retired.xsnp_miss,mem_load_uops_l3_hit_retired.xsnp_hit,mem_load_uops_l3_hit_retired.xsnp_hitm,mem_load_uops_l3_hit_retired.xsnp_none,mem_load_uops_l3_miss_retired.local_dram,uops_retired.allTX Abort InformationEventingIPLatency ValueData Source EncodingData Linear AddressIA32_PERF_GLOBAL_STATUSR9R8*RFLAGSl2_lines_out.demand_dirtyl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdbaclears.anymem_load_uops_l3_miss_retired.local_drammem_load_uops_l3_hit_retired.xsnp_nonemem_load_uops_l3_hit_retired.xsnp_hitmmem_load_uops_l3_hit_retired.xsnp_hitmem_load_uops_l3_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.l3_missmem_load_uops_retired.l2_missmem_load_uops_retired.l1_missmem_load_uops_retired.l3_hitmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uops_retired.all_storesmem_uops_retired.all_loadsmem_uops_retired.split_storesmem_uops_retired.split_loadsmem_uops_retired.lock_loadsmem_uops_retired.stlb_miss_storesmem_uops_retired.stlb_miss_loadsmem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputfp_assist.x87_inputfp_assist.x87_outputrtm_retired.aborted_misc5rtm_retired.aborted_misc4rtm_retired.aborted_misc3rtm_retired.aborted_misc2rtm_retired.aborted_misc1rtm_retired.abortedrtm_retired.commitrtm_retired.starthle_retired.aborted_misc5hle_retired.aborted_misc4hle_retired.aborted_misc3hle_retired.aborted_misc2hle_retired.aborted_misc1hle_retired.abortedhle_retired.commithle_retired.startbr_misp_retired.near_takenbr_misp_retired.all_branches_pebsbr_misp_retired.conditionalbr_inst_retired.near_call_r3br_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branches_pebsbr_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.smcmachine_clears.memory_orderingmachine_clears.countmachine_clears.cyclesuops_retired.core_stall_cyclesuops_retired.total_cyclesuops_retired.stall_cyclesuops_retired.retire_slotsuops_retired.allother_assists.any_wb_assistother_assists.sse_to_avxother_assists.avx_to_sseinst_retired.prec_disttlb_flush.stlb_anytlb_flush.dtlb_threadpage_walker_loads.itlb_memorypage_walker_loads.dtlb_memorypage_walker_loads.itlb_l3page_walker_loads.dtlb_l3page_walker_loads.itlb_l2page_walker_loads.dtlb_l2page_walker_loads.itlb_l1page_walker_loads.dtlb_l1offcore_response_1offcore_response_0uops_executed.coreuops_executed.cycles_ge_4_uops_execuops_executed.cycles_ge_3_uops_execuops_executed.cycles_ge_2_uops_execuops_executed.cycles_ge_1_uop_execuops_executed.stall_cyclesoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_code_rdoffcore_requests.demand_data_rddsb2mite_switches.penalty_cycleslsd.cycles_4_uopslsd.cycles_activelsd.uopscycle_activity.stalls_l1d_pendingcycle_activity.cycles_l1d_pendingcycle_activity.stalls_ldm_pendingcycle_activity.stalls_l2_pendingcycle_activity.cycles_no_executecycle_activity.cycles_ldm_pendingcycle_activity.cycles_l2_pendingresource_stalls.robresource_stalls.sbresource_stalls.rsresource_stalls.anyuops_executed_port.port_7_coreuops_executed_port.port_6_coreuops_executed_port.port_5_coreuops_executed_port.port_4_coreuops_executed_port.port_3_coreuops_executed_port.port_2_coreuops_executed_port.port_1_coreuops_executed_port.port_0_coreuops_executed_port.port_7uops_executed_port.port_6uops_executed_port.port_5uops_executed_port.port_4uops_executed_port.port_3uops_executed_port.port_2uops_executed_port.port_1uops_executed_port.port_0idq_uops_not_delivered.cycles_fe_was_okidq_uops_not_delivered.cycles_le_3_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_0_uops_deliv.coreidq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.taken_indirect_near_callbr_misp_exec.all_indirect_jump_non_call_retbr_misp_exec.all_conditionalbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jump_non_call_retbr_misp_exec.taken_conditionalbr_misp_exec.nontaken_conditionalbr_inst_exec.all_branchesbr_inst_exec.all_direct_near_callbr_inst_exec.all_indirect_near_returnbr_inst_exec.all_indirect_jump_non_call_retbr_inst_exec.all_direct_jmpbr_inst_exec.all_conditionalbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_indirect_near_returnbr_inst_exec.taken_indirect_jump_non_call_retbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_conditionalbr_inst_exec.nontaken_conditionalild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.stlb_hit_2mitlb_misses.stlb_hit_4kitlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.walk_completed_2m_4mitlb_misses.walk_completed_4kitlb_misses.miss_causes_a_walkicache.missesidq.mite_all_uopsidq.all_mite_cycles_any_uopsidq.all_mite_cycles_4_uopsidq.all_dsb_cycles_any_uopsidq.all_dsb_cycles_4_uopsidq.ms_dsb_occuridq.ms_dsb_cyclesidq.dsb_cyclesidq.ms_cyclesidq.ms_uopsidq.ms_mite_uopsidq.dsb_uopsidq.mite_uopsidq.emptylock_cycles.cache_lock_durationlock_cycles.split_lock_uc_lock_durationoffcore_requests_outstanding.cycles_with_data_rdoffcore_requests_outstanding.all_data_rdoffcore_requests_outstanding.demand_rfo_cyclesoffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.demand_code_rd_cyclesoffcore_requests_outstanding.demand_code_rdoffcore_requests_outstanding.cycles_with_demand_data_rdoffcore_requests_outstanding.demand_data_rdrs_events.empty_endrs_events.empty_cyclestx_exec.misc5tx_exec.misc4tx_exec.misc3tx_exec.misc2tx_exec.misc1cpl_cycles.ring123cpl_cycles.ring0_transcpl_cycles.ring0move_elimination.simd_not_eliminatedmove_elimination.int_not_eliminatedmove_elimination.simd_eliminatedmove_elimination.int_eliminatedtx_mem.abort_hle_elision_buffer_fulltx_mem.abort_hle_elision_buffer_unsupported_alignmenttx_mem.abort_hle_elision_buffer_mismatchtx_mem.abort_hle_elision_buffer_not_emptytx_mem.abort_hle_store_to_elided_locktx_mem.abort_capacity_writetx_mem.abort_conflictload_hit_pre.hw_pfload_hit_pre.sw_pfdtlb_store_misses.pde_cache_missdtlb_store_misses.stlb_hitdtlb_store_misses.stlb_hit_2mdtlb_store_misses.stlb_hit_4kdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.walk_completed_2m_4mdtlb_store_misses.walk_completed_4kdtlb_store_misses.miss_causes_a_walkl1d_pend_miss.occurencesl1d_pend_miss.pending_cyclesl1d_pend_miss.pendingl2_demand_rqsts.wb_hitl2_rqsts.referencesl2_rqsts.missl2_rqsts.all_demand_referencesl2_rqsts.all_demand_missl2_rqsts.code_rd_missl2_rqsts.code_rd_hitl2_rqsts.rfo_missl2_rqsts.rfo_hitl2_rqsts.all_code_rdl2_rqsts.all_rfol2_rqsts.all_demand_data_rdl2_rqsts.l2_pf_hitl2_rqsts.l2_pf_missl2_rqsts.demand_data_rd_hitl2_rqsts.demand_data_rd_missuops_issued.core_stall_cyclesuops_issued.stall_cyclesuops_issued.single_muluops_issued.slow_leauops_issued.flags_mergeint_misc.recovery_cycles_occurrencesint_misc.recovery_cyclesdtlb_load_misses.pde_cache_missdtlb_load_misses.stlb_hitdtlb_load_misses.stlb_hit_2mdtlb_load_misses.stlb_hit_4kdtlb_load_misses.walk_durationdtlb_load_misses.walk_completeddtlb_load_misses.walk_completed_2m_4mdtlb_load_misses.walk_completed_4kdtlb_load_misses.miss_causes_a_walkld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.store_forwardSee Chapter 19 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide" Order Number: 325384-046US, March 2013l2_lines_in.alll2_trans.l1d_wbl2_trans.all_pfitlb.itlb_flushidq.ms_switchesidq.ms_dsb_uopsidq.mite_cyclesl1d.replacementept.walk_cyclesl2_rqsts.all_pfuops_issued.anyld_blocks.no_srhle_retired.aborted,rtm_retired.abortedmem_trans_retired.load_latency,mem_uops_retired.stlb_miss_loads,mem_uops_retired.stlb_miss_stores,mem_uops_retired.lock_loads,mem_uops_retired.split_loads,mem_uops_retired.split_stores,mem_uops_retired.all_loads,mem_uops_retired.all_stores,mem_load_uops_retired.l1_hit,mem_load_uops_retired.l2_hit,mem_load_uops_retired.l3_hit,mem_load_uops_retired.l1_miss,mem_load_uops_retired.l2_miss,mem_load_uops_retired.l3_miss,mem_load_uops_retired.hit_lfb,mem_load_uops_l3_hit_retired.xsnp_miss,mem_load_uops_l3_hit_retired.xsnp_hit,mem_load_uops_l3_hit_retired.xsnp_hitm,mem_load_uops_l3_hit_retired.xsnp_none,mem_load_uops_l3_miss_retired.local_dram,mem_load_uops_l3_miss_retired.remote_dram,mem_load_uops_l3_miss_retired.remote_hitm,mem_load_uops_l3_miss_retired.remote_fwd,uops_retired.alll2_lines_out.demand_dirtyl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdbaclears.anymem_load_l4_miss_retired.local_missmem_load_l4_miss_retired.local_hitmem_load_uops_l3_miss_retired.remote_fwdmem_load_uops_l3_miss_retired.remote_hitmmem_load_uops_l3_miss_retired.remote_drammem_load_uops_l3_miss_retired.local_drammem_load_uops_l3_hit_retired.xsnp_nonemem_load_uops_l3_hit_retired.xsnp_hitmmem_load_uops_l3_hit_retired.xsnp_hitmem_load_uops_l3_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.l3_missmem_load_uops_retired.l2_missmem_load_uops_retired.l1_missmem_load_uops_retired.l3_hitmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uops_retired.all_storesmem_uops_retired.all_loadsmem_uops_retired.split_storesmem_uops_retired.split_loadsmem_uops_retired.lock_loadsmem_uops_retired.stlb_miss_storesmem_uops_retired.stlb_miss_loadsmem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputfp_assist.x87_inputfp_assist.x87_outputrtm_retired.aborted_misc5rtm_retired.aborted_misc4rtm_retired.aborted_misc3rtm_retired.aborted_misc2rtm_retired.aborted_misc1rtm_retired.abortedrtm_retired.commitrtm_retired.starthle_retired.aborted_misc5hle_retired.aborted_misc4hle_retired.aborted_misc3hle_retired.aborted_misc2hle_retired.aborted_misc1hle_retired.abortedhle_retired.commithle_retired.startbr_misp_retired.near_takenbr_misp_retired.all_branches_pebsbr_misp_retired.conditionalbr_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branches_pebsbr_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.smcmachine_clears.memory_orderingmachine_clears.cyclesmachine_clears.countuops_retired.retire_slotsuops_retired.total_cyclesuops_retired.stall_cyclesuops_retired.core_stall_cyclesuops_retired.allother_assists.any_wb_assistother_assists.sse_to_avxother_assists.avx_to_sseinst_retired.prec_disttlb_flush.stlb_anytlb_flush.dtlb_threadpage_walker_loads.ept_itlb_memorypage_walker_loads.ept_itlb_l3page_walker_loads.ept_itlb_l2page_walker_loads.ept_itlb_l1page_walker_loads.ept_dtlb_memorypage_walker_loads.ept_dtlb_l3page_walker_loads.ept_dtlb_l2page_walker_loads.ept_dtlb_l1page_walker_loads.itlb_memorypage_walker_loads.itlb_l3page_walker_loads.itlb_l2page_walker_loads.itlb_l1page_walker_loads.dtlb_memorypage_walker_loads.dtlb_l3page_walker_loads.dtlb_l2page_walker_loads.dtlb_l1offcore_response_1offcore_response_0uops_executed.coreuops_executed.stall_cyclesuops_executed.cycles_ge_4_uops_execuops_executed.cycles_ge_3_uops_execuops_executed.cycles_ge_2_uops_execuops_executed.cycles_ge_1_uop_execoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_code_rdoffcore_requests.demand_data_rddsb2mite_switches.penalty_cycleslsd.uopscycle_activity.stalls_l1d_pendingcycle_activity.cycles_l1d_pendingcycle_activity.stalls_ldm_pendingcycle_activity.stalls_l2_pendingcycle_activity.cycles_no_executecycle_activity.cycles_ldm_pendingcycle_activity.cycles_l2_pendingresource_stalls.robresource_stalls.sbresource_stalls.rsresource_stalls.anyuops_executed_port.port_7_coreuops_executed_port.port_7uops_executed_port.port_6_coreuops_executed_port.port_6uops_executed_port.port_5_coreuops_executed_port.port_5uops_executed_port.port_4_coreuops_executed_port.port_4uops_executed_port.port_3_coreuops_executed_port.port_3uops_executed_port.port_2_coreuops_executed_port.port_2uops_executed_port.port_1_coreuops_executed_port.port_1uops_executed_port.port_0_coreuops_executed_port.port_0idq_uops_not_delivered.cycles_le_3_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_fe_was_okidq_uops_not_delivered.cycles_0_uops_deliv.coreidq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.all_indirect_jump_non_call_retbr_misp_exec.all_conditionalbr_misp_exec.taken_indirect_near_callbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jump_non_call_retbr_misp_exec.taken_conditionalbr_misp_exec.nontaken_conditionalbr_inst_exec.all_branchesbr_inst_exec.all_direct_near_callbr_inst_exec.all_indirect_near_returnbr_inst_exec.all_indirect_jump_non_call_retbr_inst_exec.all_direct_jmpbr_inst_exec.all_conditionalbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_indirect_near_returnbr_inst_exec.taken_indirect_jump_non_call_retbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_conditionalbr_inst_exec.nontaken_conditionalild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.stlb_hit_2mitlb_misses.stlb_hit_4kitlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.walk_completed_2m_4mitlb_misses.walk_completed_4kitlb_misses.miss_causes_a_walkicache.ifetch_stallicache.missesidq.mite_all_uopsidq.ms_uopsidq.ms_cyclesidq.all_mite_cycles_any_uopsidq.all_mite_cycles_4_uopsidq.ms_mite_uopsidq.all_dsb_cycles_any_uopsidq.all_dsb_cycles_4_uopsidq.ms_dsb_occuridq.ms_dsb_cyclesidq.dsb_uopsidq.dsb_cyclesidq.mite_uopsidq.emptylock_cycles.cache_lock_durationlock_cycles.split_lock_uc_lock_durationoffcore_requests_outstanding.cycles_with_data_rdoffcore_requests_outstanding.all_data_rdoffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.demand_code_rdoffcore_requests_outstanding.demand_data_rdoffcore_requests_outstanding.cycles_with_demand_data_rdrs_events.empty_endrs_events.empty_cyclestx_exec.misc5tx_exec.misc4tx_exec.misc3tx_exec.misc2tx_exec.misc1cpl_cycles.ring123cpl_cycles.ring0_transcpl_cycles.ring0move_elimination.simd_not_eliminatedmove_elimination.int_not_eliminatedmove_elimination.simd_eliminatedmove_elimination.int_eliminatedtx_mem.hle_elision_buffer_fulltx_mem.abort_hle_elision_buffer_unsupported_alignmenttx_mem.abort_hle_elision_buffer_mismatchtx_mem.abort_hle_elision_buffer_not_emptytx_mem.abort_hle_store_to_elided_locktx_mem.abort_capacity_writetx_mem.abort_conflictload_hit_pre.hw_pfload_hit_pre.sw_pfdtlb_store_misses.pde_cache_missdtlb_store_misses.stlb_hitdtlb_store_misses.stlb_hit_2mdtlb_store_misses.stlb_hit_4kdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.walk_completed_2m_4mdtlb_store_misses.walk_completed_4kdtlb_store_misses.miss_causes_a_walkl1d_pend_miss.pending_cyclesl1d_pend_miss.pendingl2_demand_rqsts.wb_hitl2_rqsts.referencesl2_rqsts.all_demand_referencesl2_rqsts.all_code_rdl2_rqsts.all_rfol2_rqsts.all_demand_data_rdl2_rqsts.l2_pf_hitl2_rqsts.code_rd_hitl2_rqsts.rfo_hitl2_rqsts.demand_data_rd_hitl2_rqsts.missl2_rqsts.l2_pf_missl2_rqsts.all_demand_missl2_rqsts.code_rd_missl2_rqsts.rfo_missl2_rqsts.demand_data_rd_missuops_issued.single_muluops_issued.slow_leauops_issued.flags_mergeuops_issued.core_stall_cyclesuops_issued.stall_cyclesint_misc.recovery_cyclesdtlb_load_misses.pde_cache_missdtlb_load_misses.stlb_hitdtlb_load_misses.stlb_hit_2mdtlb_load_misses.stlb_hit_4kdtlb_load_misses.walk_durationdtlb_load_misses.walk_completeddtlb_load_misses.walk_completed_2m_4mdtlb_load_misses.walk_completed_4kdtlb_load_misses.miss_causes_a_walkld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.store_forwardSee Chapter 19 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide" Order Number: 325384-052US, September 2014R15R14R13R12R11R10RSPRBPRDIRSIRDXRCXRBXRAXRIPl2_lines_in.alll2_trans.l1d_wbl2_trans.all_pfitlb.itlb_flushidq.ms_switchesidq.ms_dsb_uopsidq.mite_cyclesl1d.replacementept.walk_cyclesl2_rqsts.all_pfuops_issued.anyld_blocks.no_srhle_retired.aborted,rtm_retired.abortedmem_trans_retired.load_latency,mem_uops_retired.lock_stores,mem_uops_retired.stlb_miss_loads,mem_uops_retired.stlb_miss_stores,mem_uops_retired.lock_loads,mem_uops_retired.split_loads,mem_uops_retired.split_stores,mem_uops_retired.all_loads,mem_uops_retired.all_stores,mem_load_uops_retired.l1_hit,mem_load_uops_retired.l2_hit,mem_load_uops_retired.l3_hit,mem_load_uops_retired.l1_miss,mem_load_uops_retired.l2_miss,mem_load_uops_retired.l3_miss,mem_load_uops_retired.hit_lfb,mem_load_uops_l3_hit_retired.xsnp_miss,mem_load_uops_l3_hit_retired.xsnp_hit,mem_load_uops_l3_hit_retired.xsnp_hitm,mem_load_uops_l3_hit_retired.xsnp_none,mem_load_uops_l3_miss_retired.local_dram,uops_retired.allTX Abort InformationEventingIPLatency ValueData Source EncodingData Linear AddressIA32_PERF_GLOBAL_STATUSR9R8*RFLAGSl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdbaclears.anymem_load_l4_miss_retired.local_missmem_load_l4_miss_retired.local_hitmem_load_uops_l3_miss_retired.local_drammem_load_uops_l3_hit_retired.xsnp_nonemem_load_uops_l3_hit_retired.xsnp_hitmmem_load_uops_l3_hit_retired.xsnp_hitmem_load_uops_l3_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.l3_missmem_load_uops_retired.l2_missmem_load_uops_retired.l1_missmem_load_uops_retired.l3_hitmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uops_retired.all_storesmem_uops_retired.all_loadsmem_uops_retired.split_storesmem_uops_retired.split_loadsmem_uops_retired.lock_storesmem_uops_retired.lock_loadsmem_uops_retired.stlb_miss_storesmem_uops_retired.stlb_miss_loadsmem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputfp_assist.x87_inputfp_assist.x87_outputrtm_retired.aborted_misc5rtm_retired.aborted_misc4rtm_retired.aborted_misc3rtm_retired.aborted_misc2rtm_retired.aborted_misc1rtm_retired.abortedrtm_retired.commitrtm_retired.starthle_retired.aborted_misc5hle_retired.aborted_misc4hle_retired.aborted_misc3hle_retired.aborted_misc2hle_retired.aborted_misc1hle_retired.abortedhle_retired.commithle_retired.startfp_arith_inst_retired.256b_packed_singlefp_arith_inst_retired.256b_packed_doublefp_arith_inst_retired.128b_packed_singlefp_arith_inst_retired.128b_packed_doublefp_arith_inst_retired.scalar_singlefp_arith_inst_retired.scalar_doublebr_misp_retired.near_takenbr_misp_retired.all_branches_pebsbr_misp_retired.conditionalbr_inst_retired.near_call_r3br_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branches_pebsbr_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.smcmachine_clears.memory_orderingmachine_clears.countmachine_clears.cyclesuops_retired.core_stall_cyclesuops_retired.total_cyclesuops_retired.stall_cyclesuops_retired.retire_slotsuops_retired.allother_assists.any_wb_assistother_assists.sse_to_avxother_assists.avx_to_sseinst_retired.x87inst_retired.prec_disttlb_flush.stlb_anytlb_flush.dtlb_threadpage_walker_loads.dtlb_memorypage_walker_loads.itlb_l3page_walker_loads.dtlb_l3page_walker_loads.itlb_l2page_walker_loads.dtlb_l2page_walker_loads.itlb_l1page_walker_loads.dtlb_l1offcore_response_1offcore_response_0offcore_requests_buffer.sq_fulluops_executed.cycles_ge_4_uops_execuops_executed.cycles_ge_3_uops_execuops_executed.cycles_ge_2_uops_execuops_executed.cycles_ge_1_uop_execuops_executed.stall_cyclesuops_executed.coreuops_executed.threadoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_code_rdoffcore_requests.demand_data_rddsb2mite_switches.penalty_cycleslsd.cycles_4_uopslsd.cycles_activelsd.uopscycle_activity.stalls_l1d_pendingcycle_activity.cycles_l1d_pendingcycle_activity.stalls_ldm_pendingcycle_activity.stalls_l2_pendingcycle_activity.cycles_no_executecycle_activity.cycles_ldm_pendingcycle_activity.cycles_l2_pendingresource_stalls.robresource_stalls.sbresource_stalls.rsresource_stalls.anyuops_executed_port.port_7_coreuops_executed_port.port_6_coreuops_executed_port.port_5_coreuops_executed_port.port_4_coreuops_executed_port.port_3_coreuops_executed_port.port_2_coreuops_executed_port.port_1_coreuops_executed_port.port_0_coreuops_executed_port.port_7uops_executed_port.port_6uops_executed_port.port_5uops_executed_port.port_4uops_executed_port.port_3uops_executed_port.port_2uops_executed_port.port_1uops_executed_port.port_0uop_dispatches_cancelled.simd_prfidq_uops_not_delivered.cycles_fe_was_okidq_uops_not_delivered.cycles_le_3_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_0_uops_deliv.coreidq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.taken_indirect_near_callbr_misp_exec.all_indirect_jump_non_call_retbr_misp_exec.all_conditionalbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jump_non_call_retbr_misp_exec.taken_conditionalbr_misp_exec.nontaken_conditionalbr_inst_exec.all_branchesbr_inst_exec.all_direct_near_callbr_inst_exec.all_indirect_near_returnbr_inst_exec.all_indirect_jump_non_call_retbr_inst_exec.all_direct_jmpbr_inst_exec.all_conditionalbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_indirect_near_returnbr_inst_exec.taken_indirect_jump_non_call_retbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_conditionalbr_inst_exec.nontaken_conditionalild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.stlb_hit_2mitlb_misses.stlb_hit_4kitlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.walk_completed_2m_4mitlb_misses.walk_completed_4kitlb_misses.miss_causes_a_walkicache.missesicache.hitidq.mite_all_uopsidq.ms_cyclesidq.ms_uopsidq.all_mite_cycles_any_uopsidq.all_mite_cycles_4_uopsidq.ms_mite_uopsidq.all_dsb_cycles_any_uopsidq.all_dsb_cycles_4_uopsidq.ms_dsb_occuridq.ms_dsb_cyclesidq.dsb_cyclesidq.dsb_uopsidq.mite_uopsidq.emptylock_cycles.cache_lock_durationlock_cycles.split_lock_uc_lock_durationoffcore_requests_outstanding.cycles_with_data_rdoffcore_requests_outstanding.all_data_rdoffcore_requests_outstanding.demand_rfo_cyclesoffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.demand_code_rd_cyclesoffcore_requests_outstanding.demand_code_rdoffcore_requests_outstanding.cycles_with_demand_data_rdoffcore_requests_outstanding.demand_data_rdrs_events.empty_endrs_events.empty_cyclestx_exec.misc5tx_exec.misc4tx_exec.misc3tx_exec.misc2tx_exec.misc1cpl_cycles.ring123cpl_cycles.ring0_transcpl_cycles.ring0move_elimination.simd_not_eliminatedmove_elimination.int_not_eliminatedmove_elimination.simd_eliminatedmove_elimination.int_eliminatedtx_mem.hle_elision_buffer_fulltx_mem.abort_hle_elision_buffer_unsupported_alignmenttx_mem.abort_hle_elision_buffer_mismatchtx_mem.abort_hle_elision_buffer_not_emptytx_mem.abort_hle_store_to_elided_locktx_mem.abort_capacity_writetx_mem.abort_conflictload_hit_pre.hw_pfload_hit_pre.sw_pfdtlb_store_misses.pde_cache_missdtlb_store_misses.stlb_hitdtlb_store_misses.stlb_hit_2mdtlb_store_misses.stlb_hit_4kdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.walk_completed_2m_4mdtlb_store_misses.walk_completed_4kdtlb_store_misses.miss_causes_a_walkl1d_pend_miss.occurencesl1d_pend_miss.pending_cyclesl1d_pend_miss.pendingcpu_clk_thread_unhalted.one_thread_activel2_demand_rqsts.wb_hitl2_rqsts.referencesl2_rqsts.missl2_rqsts.all_demand_referencesl2_rqsts.all_demand_missl2_rqsts.code_rd_missl2_rqsts.code_rd_hitl2_rqsts.rfo_missl2_rqsts.rfo_hitl2_rqsts.all_code_rdl2_rqsts.all_rfol2_rqsts.all_demand_data_rdl2_rqsts.l2_pf_hitl2_rqsts.l2_pf_missl2_rqsts.demand_data_rd_hitl2_rqsts.demand_data_rd_missarith.fpu_div_activeuops_issued.core_stall_cyclesuops_issued.stall_cyclesuops_issued.single_muluops_issued.slow_leauops_issued.flags_mergeint_misc.rat_stall_cyclesint_misc.recovery_cycles_occurrencesint_misc.recovery_cyclesdtlb_load_misses.pde_cache_missdtlb_load_misses.stlb_hitdtlb_load_misses.stlb_hit_2mdtlb_load_misses.stlb_hit_4kdtlb_load_misses.walk_durationdtlb_load_misses.walk_completeddtlb_load_misses.walk_completed_2m_4mdtlb_load_misses.walk_completed_4kdtlb_load_misses.miss_causes_a_walkld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.store_forwardSee Chapter 19 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide" Order Number: 325462-053US, January 2015l2_lines_in.alll2_trans.l1d_wbl2_trans.all_pfitlb.itlb_flushidq.ms_switchesidq.ms_dsb_uopsidq.mite_cyclesl1d.replacementept.walk_cyclesl2_rqsts.all_pfuops_issued.anyld_blocks.no_srhle_retired.aborted,rtm_retired.abortedmem_trans_retired.load_latency,mem_uops_retired.lock_stores,mem_uops_retired.stlb_miss_loads,mem_uops_retired.stlb_miss_stores,mem_uops_retired.lock_loads,mem_uops_retired.split_loads,mem_uops_retired.split_stores,mem_uops_retired.all_loads,mem_uops_retired.all_stores,mem_load_uops_retired.l1_hit,mem_load_uops_retired.l2_hit,mem_load_uops_retired.l3_hit,mem_load_uops_retired.l1_miss,mem_load_uops_retired.l2_miss,mem_load_uops_retired.l3_miss,mem_load_uops_retired.hit_lfb,mem_load_uops_l3_hit_retired.xsnp_miss,mem_load_uops_l3_hit_retired.xsnp_hit,mem_load_uops_l3_hit_retired.xsnp_hitm,mem_load_uops_l3_hit_retired.xsnp_none,mem_load_uops_l3_miss_retired.local_dram,mem_load_uops_l3_miss_retired.remote_dram,mem_load_uops_l3_miss_retired.remote_hitm,mem_load_uops_l3_miss_retired.remote_fwd,uops_retired.alll2_lines_out.demand_dirtyl2_lines_out.demand_cleanl2_lines_in.el2_lines_in.sl2_lines_in.il2_trans.all_requestsl2_trans.l2_wbl2_trans.l2_filll2_trans.code_rdl2_trans.rfol2_trans.demand_data_rdbaclears.anymem_load_uops_l3_miss_retired.local_drammem_load_uops_l3_hit_retired.xsnp_nonemem_load_uops_l3_hit_retired.xsnp_hitmmem_load_uops_l3_hit_retired.xsnp_hitmem_load_uops_l3_hit_retired.xsnp_missmem_load_uops_retired.hit_lfbmem_load_uops_retired.l3_missmem_load_uops_retired.l2_missmem_load_uops_retired.l1_missmem_load_uops_retired.l3_hitmem_load_uops_retired.l2_hitmem_load_uops_retired.l1_hitmem_uops_retired.all_storesmem_uops_retired.all_loadsmem_uops_retired.split_storesmem_uops_retired.split_loadsmem_uops_retired.lock_storesmem_uops_retired.lock_loadsmem_uops_retired.stlb_miss_storesmem_uops_retired.stlb_miss_loadsmem_trans_retired.load_latencyrob_misc_events.lbr_insertsfp_assist.anyfp_assist.simd_inputfp_assist.simd_outputfp_assist.x87_inputfp_assist.x87_outputrtm_retired.aborted_misc5rtm_retired.aborted_misc4rtm_retired.aborted_misc3rtm_retired.aborted_misc2rtm_retired.aborted_misc1rtm_retired.abortedrtm_retired.commitrtm_retired.starthle_retired.aborted_misc5hle_retired.aborted_misc4hle_retired.aborted_misc3hle_retired.aborted_misc2hle_retired.aborted_misc1hle_retired.abortedhle_retired.commithle_retired.startfp_arith_inst_retired.packedfp_arith_inst_retired.doublefp_arith_inst_retired.256b_packed_singlefp_arith_inst_retired.singlefp_arith_inst_retired.256b_packed_doublefp_arith_inst_retired.128b_packed_singlefp_arith_inst_retired.128b_packed_doublefp_arith_inst_retired.scalarfp_arith_inst_retired.scalar_singlefp_arith_inst_retired.scalar_doublebr_misp_retired.near_takenbr_misp_retired.all_branches_pebsbr_misp_retired.conditionalbr_inst_retired.near_call_r3br_inst_retired.far_branchbr_inst_retired.near_takenbr_inst_retired.not_takenbr_inst_retired.near_returnbr_inst_retired.all_branches_pebsbr_inst_retired.near_callbr_inst_retired.conditionalmachine_clears.maskmovmachine_clears.smcmachine_clears.memory_orderingmachine_clears.countuops_retired.core_stall_cyclesuops_retired.total_cyclesuops_retired.stall_cyclesuops_retired.retire_slotsuops_retired.allother_assists.any_wb_assistother_assists.sse_to_avxother_assists.avx_to_sseinst_retired.prec_disttlb_flush.stlb_anytlb_flush.dtlb_threadpage_walker_loads.itlb_memorypage_walker_loads.dtlb_memorypage_walker_loads.itlb_l3page_walker_loads.dtlb_l3page_walker_loads.itlb_l2page_walker_loads.dtlb_l2page_walker_loads.itlb_l1page_walker_loads.dtlb_l1offcore_response_1offcore_response_0offcore_requests_buffer.sq_fulluops_executed.core_cycles_ge_4uops_executed.core_cycles_ge_3uops_executed.core_cycles_ge_2uops_executed.core_cycles_ge_1uops_executed.core_cycles_noneuops_executed.cycles_ge_4_uops_execuops_executed.cycles_ge_3_uops_execuops_executed.cycles_ge_2_uops_execuops_executed.cycles_ge_1_uop_execuops_executed.stall_cyclesuops_executed.coreuops_executed.threadoffcore_requests.all_data_rdoffcore_requests.demand_rfooffcore_requests.demand_code_rdoffcore_requests.demand_data_rddsb2mite_switches.penalty_cycleslsd.cycles_4_uopslsd.cycles_activelsd.uopscycle_activity.stalls_l1d_pendingcycle_activity.cycles_l1d_pendingcycle_activity.stalls_ldm_pendingcycle_activity.stalls_l2_pendingcycle_activity.cycles_no_executecycle_activity.cycles_ldm_pendingresource_stalls.robresource_stalls.sbresource_stalls.rsresource_stalls.anyuops_executed_port.port_7_coreuops_executed_port.port_6_coreuops_executed_port.port_5_coreuops_executed_port.port_4_coreuops_executed_port.port_3_coreuops_executed_port.port_2_coreuops_executed_port.port_1_coreuops_executed_port.port_0_coreuops_executed_port.port_7uops_executed_port.port_6uops_executed_port.port_5uops_executed_port.port_4uops_executed_port.port_3uops_executed_port.port_2uops_executed_port.port_1uops_executed_port.port_0uop_dispatches_cancelled.simd_prfidq_uops_not_delivered.cycles_fe_was_okidq_uops_not_delivered.cycles_le_3_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_0_uops_deliv.coreidq_uops_not_delivered.corebr_misp_exec.all_branchesbr_misp_exec.taken_indirect_near_callbr_misp_exec.all_indirect_jump_non_call_retbr_misp_exec.all_conditionalbr_misp_exec.taken_return_nearbr_misp_exec.taken_indirect_jump_non_call_retbr_misp_exec.taken_conditionalbr_misp_exec.nontaken_conditionalbr_inst_exec.all_branchesbr_inst_exec.all_direct_near_callbr_inst_exec.all_indirect_near_returnbr_inst_exec.all_indirect_jump_non_call_retbr_inst_exec.all_direct_jmpbr_inst_exec.all_conditionalbr_inst_exec.taken_indirect_near_callbr_inst_exec.taken_direct_near_callbr_inst_exec.taken_indirect_near_returnbr_inst_exec.taken_indirect_jump_non_call_retbr_inst_exec.taken_direct_jumpbr_inst_exec.taken_conditionalbr_inst_exec.nontaken_conditionalild_stall.iq_fullild_stall.lcpitlb_misses.stlb_hititlb_misses.stlb_hit_2mitlb_misses.stlb_hit_4kitlb_misses.walk_durationitlb_misses.walk_completeditlb_misses.walk_completed_2m_4mitlb_misses.walk_completed_4kitlb_misses.miss_causes_a_walkicache.ifdata_stallicache.missesicache.hitidq.mite_all_uopsidq.ms_cyclesidq.ms_uopsidq.all_mite_cycles_any_uopsidq.all_mite_cycles_4_uopsidq.ms_mite_uopsidq.all_dsb_cycles_any_uopsidq.all_dsb_cycles_4_uopsidq.ms_dsb_occuridq.ms_dsb_cyclesidq.dsb_cyclesidq.dsb_uopsidq.mite_uopsidq.emptylock_cycles.cache_lock_durationlock_cycles.split_lock_uc_lock_durationoffcore_requests_outstanding.cycles_with_data_rdoffcore_requests_outstanding.all_data_rdoffcore_requests_outstanding.demand_rfo_cyclesoffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.demand_code_rd_cyclesoffcore_requests_outstanding.demand_code_rdoffcore_requests_outstanding.demand_data_rd_ge_6offcore_requests_outstanding.cycles_with_demand_data_rdoffcore_requests_outstanding.demand_data_rdrs_events.empty_endrs_events.empty_cyclestx_exec.misc5tx_exec.misc4tx_exec.misc3tx_exec.misc2tx_exec.misc1cpl_cycles.ring123cpl_cycles.ring0_transcpl_cycles.ring0move_elimination.simd_not_eliminatedmove_elimination.int_not_eliminatedmove_elimination.simd_eliminatedmove_elimination.int_eliminatedtx_mem.hle_elision_buffer_fulltx_mem.abort_hle_elision_buffer_unsupported_alignmenttx_mem.abort_hle_elision_buffer_mismatchtx_mem.abort_hle_elision_buffer_not_emptytx_mem.abort_hle_store_to_elided_locktx_mem.abort_capacity_writetx_mem.abort_conflictload_hit_pre.hw_pfload_hit_pre.sw_pfdtlb_store_misses.pde_cache_missdtlb_store_misses.stlb_hitdtlb_store_misses.stlb_hit_2mdtlb_store_misses.stlb_hit_4kdtlb_store_misses.walk_durationdtlb_store_misses.walk_completeddtlb_store_misses.walk_completed_2m_4mdtlb_store_misses.walk_completed_4kdtlb_store_misses.miss_causes_a_walkl1d_pend_miss.fb_fulll1d_pend_miss.pending_cycles_anyl1d_pend_miss.occurencesl1d_pend_miss.pending_cyclesl1d_pend_miss.pendingcpu_clk_thread_unhalted.one_thread_activecpu_clk_thread_unhalted.ref_xclk_anycpu_clk_unhalted.thread_p_anyl2_demand_rqsts.wb_hitl2_rqsts.referencesl2_rqsts.missl2_rqsts.all_demand_referencesl2_rqsts.all_demand_missl2_rqsts.code_rd_missl2_rqsts.code_rd_hitl2_rqsts.rfo_missl2_rqsts.rfo_hitl2_rqsts.all_code_rdl2_rqsts.all_rfol2_rqsts.all_demand_data_rdl2_rqsts.l2_pf_hitl2_rqsts.l2_pf_missl2_rqsts.demand_data_rd_hitl2_rqsts.demand_data_rd_missuops_issued.core_stall_cyclesuops_issued.stall_cyclesuops_issued.single_muluops_issued.slow_leauops_issued.flags_mergeint_misc.rat_stall_cyclesint_misc.recovery_cycles_occurrencesint_misc.recovery_cycles_anyint_misc.recovery_cyclesdtlb_load_misses.pde_cache_missdtlb_load_misses.stlb_hitdtlb_load_misses.stlb_hit_2mdtlb_load_misses.stlb_hit_4kdtlb_load_misses.walk_durationdtlb_load_misses.walk_completeddtlb_load_misses.walk_completed_2m_4mdtlb_load_misses.walk_completed_4kdtlb_load_misses.miss_causes_a_walkld_blocks_partial.address_aliasmisalign_mem_ref.storesmisalign_mem_ref.loadsld_blocks.store_forwardsb_forwards.store_forwardsSee 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