'\" te
.\" Copyright (c) 2012, 2015, Oracle and/or its affiliates. All rights                reserved
.TH as 1 "07 Apr 2015" "SunOS 5.11" "User Commands"
.SH NAME
as \- assembler
.SH SYNOPSIS
.LP
.nf
SPARC
.fi

.LP
.nf
\fBas\fR [ \fB-hwcap\fR={1|0} ] [ \fB-L\fR ] [ \fB-m\fR ] [ \fB-m32\fR ] [ \fB-m64\fR ]
     [ \fB-n\fR ] [ \fB-o\fR \fIoutfile\fR ] [ \fB-ul\fR ] [ \fB-P\fR ]
     [ \fB-D\fR\fIname\fR ] [ \fB-D\fR\fIname\fR=\fIdef\fR ] [ \fB-I\fR\fIpath\fR ]
     [ \fB-U\fR\fIname\fR....  ] [ \fB-Q\fR[y|n] ] [ \fB-s\fR ]
     [ \fB-S\fR[a|b|c|l|A|B|C|L]] [ \fB-V\fR ] [ \fB-x\fRarch=\fIv\fR ]
     [ \fB-xF\fR ] [ \fB-Y\fR[m|c],\fIpath\fR ] [ \fB-YI\fR,\fIpath\fR ] \fIfilename\fR...
.fi

.LP
.nf
x86
.fi

.LP
.nf
\fBas\fR [ \fB-a32\fR ] [ \fB-m\fR ] [ \fB-m32\fR ] [ \fB-m64\fR ] [ \fB-n\fR ]
     [ \fB-H\fR ] [ \fB-nH\fR ] [ \fB-o\fR \fIoutfile\fR ]
     [ \fB-P\fR ] [ \fB-D\fR\fIname\fR ] [ \fB-D\fR\fIname\fR=\fIdef\fR ] [ \fB-I\fR\fIpath\fR ]
     [ \fB-U\fR\fIname\fR....  ]
     [ \fB-KPIC\fR ] [ \fB-Q\fR[y|n] ] [ \fB-s\fR ] [ \fB-S\fR[a|b|c|l|A|B|C|L]] [ \fB-V\fR ]
     [ \fB-xchip\fR=\fIv\fR ] [ \fB-xmodel\fR=[\fIa\fR] ]
     [ \fB-Y\fR[m|d],\fIpath\fR ] [ \fB-YI\fR,\fIpath\fR ] \fIfilename\fR...
.fi

.SH DESCRIPTION
.sp
.LP
The \fBas\fR command creates object files from assembly language source files.
.SH OPTIONS
.sp
.LP
This section is divided into three:
.RS +4
.TP
.ie t \(bu
.el o
Common Options (options common to both SPARC and x86)
.RE
.RS +4
.TP
.ie t \(bu
.el o
SPARC Options
.RE
.RS +4
.TP
.ie t \(bu
.el o
x86 Options
.RE
.SS "Common Options"
.sp
.ne 2
.mk
.na
\fB\fB-D\fR\fIname\fR\fR
.ad
.br
.na
\fB\fB-D\fR\fIname\fR=\fIdef\fR\fR
.ad
.sp .6
.RS 4n
When the \fB-P\fR option is in effect, these options are passed to the \fBcpp\fR(1) preprocessor without interpretation by the \fBas\fR command; otherwise, they are ignored.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-I\fR \fIpath\fR\fR
.ad
.sp .6
.RS 4n
When the \fB-P\fR option is in effect, this option is passed to the \fBcpp\fR(1) preprocessor without interpretation by the \fBas\fR command; otherwise, it is ignored.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-i\fR\fR
.ad
.sp .6
.RS 4n
Instructs \fBas\fR to ignore line-number information from the preprocessor.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-m\fR\fR
.ad
.sp .6
.RS 4n
Run the \fBm4\fR(1) macro processor on the input to the assembler.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-m32\fR|\fB-m64\fR\fR
.ad
.sp .6
.RS 4n
Generate 32-bit or 64-bit ELF format object code.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-n\fR\fR
.ad
.sp .6
.RS 4n
Suppress all the warnings while assembling.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-o\fR \fIoutfile\fR\fR
.ad
.sp .6
.RS 4n
Put the output of the assembly in \fIoutfile\fR. By default, the output file name is formed by removing the \fB\&.s\fR suffix, if there is one, from the input file name and appending an \fB\&.o\fR suffix.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-P\fR\fR
.ad
.sp .6
.RS 4n
Run \fBcpp\fR(1), the C preprocessor, on the files being assembled. The preprocessor is run separately on each input file, not on their con- catenation. The preprocessor output is passed to the assembler.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-Q\fR[\fBy\fR|\fBn\fR]\fR
.ad
.sp .6
.RS 4n
If the \fBy\fR option is specified, it produces the "assembler version" information in the comment section of the output object file. If the \fBn\fR option is specified, the information is suppressed.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-S\fR[\fBa\fR|\fBb\fR|\fBc\fR|\fBl\fR|\fBA\fR|\fBB\fR|\fBC\fR|\fBL\fR]\fR
.ad
.sp .6
.RS 4n
Produces a disassembly of the emitted code to the standard output. Adding each of the following characters to the \fB-S\fR option produces:
.sp
.ne 2
.mk
.na
\fB\fBa\fR\fR
.ad
.RS 5n
.rt  
Disassembling with address
.RE

.sp
.ne 2
.mk
.na
\fB\fBb\fR\fR
.ad
.RS 5n
.rt  
Disassembling with \fB\&.bof\fR
.RE

.sp
.ne 2
.mk
.na
\fB\fBc\fR\fR
.ad
.RS 5n
.rt  
Disassembling with comments
.RE

.sp
.ne 2
.mk
.na
\fB\fBl\fR\fR
.ad
.RS 5n
.rt  
Disassembling with line numbers.
.RE

Capital letters switch the corresponding option off. The default is \fB-Sc\fR.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-s\fR\fR
.ad
.sp .6
.RS 4n
Place all stabs in the \fB\&.stabs\fR section. By default, stabs are placed in \fBstabs.excl\fR sections, which are stripped out by the static linker, \fBld\fR(1), during final execution. When the \fB-s\fR option is used, stabs remain in the final executable because \fB\&.stab\fR sections are not stripped by the static linker.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-U\fR\fIname\fR\fR
.ad
.sp .6
.RS 4n
When the \fB-P\fR option is in effect, this option is passed to the \fBcpp\fR(1) preprocessor without interpretation by the \fBas\fR command; otherwise, it is ignored.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-Ym\fR,\fIpath\fR\fR
.ad
.sp .6
.RS 4n
Specify path to the version of \fBm4\fR to use.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-YI\fR,\fIpath\fR\fR
.ad
.sp .6
.RS 4n
Indicate path to search for \fB#include\fR header files.
.RE

.SS "SPARC Options"
.sp
.ne 2
.mk
.na
\fB\fB-hwcap\fR={\fB1|0\fR}\fR
.ad
.sp .6
.RS 4n
Enable (\fB1\fR) or suppress (\fB0\fR) the generation of the Hardware Capabilities section. Default is to generate the section.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-L\fR\fR
.ad
.sp .6
.RS 4n
Save all symbols, including temporary labels that are normally discarded to save space, in the ELF symbol table.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-ul\fR\fR
.ad
.sp .6
.RS 4n
Treat all undefined symbols as local.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-Yc\fR,\fIpath\fR\fR
.ad
.sp .6
.RS 4n
Specify path to the version of \fBcpp\fR to use.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparc\fR\fR
.ad
.sp .6
.RS 4n
Enables the assembler to accept instructions defined in the SPARC-V9 architecture. The resulting object code is in ELF32 format when compiled with \fB-m32\fR, ELF64 format with \fB-m64\fR. It will not execute on a Oracle Solaris V8 system (a machine with a V8 processor). It will execute on a Oracle Solaris V8+ system.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparcvis\fR\fR
.ad
.sp .6
.RS 4n
Enables the assembler to accept instructions defined in the SPARC-V9 architecture plus the instructions in the Visual Instruction Set (VIS) version 1.0. The resulting object code is in V8+ ELF32 format when compiled with \fB-m32\fR, ELF64 format with \fB-m64\fR. It will not execute on a Oracle Solaris system with a V8 processor. It will execute on a Oracle Solaris system with a V8+ processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparcvis2\fR\fR
.ad
.sp .6
.RS 4n
Enables the assembler to accept instructions defined in the SPARC-V9 architecture, plus the instructions in the Visual Instruction Set (VIS) version 2.0, with UltraSPARC-III extensions. The resulting object code is in V8+ ELF32 format when compiled with \fB-m32\fR, ELF64 format with \fB-m64\fR.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparcvis3\fR\fR
.ad
.sp .6
.RS 4n
Accept instructions defined for the SPARC VIS version 3 of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the fused multiply-add instructions, and the Visual Instruction Set (VIS) version 3.0.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparcfmaf\fR\fR
.ad
.sp .6
.RS 4n
Accept instructions defined for the \fBsparcfmaf\fR version of the SPARC-V9 ISA, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, and the SPARC64 VI extensions for floating-point multiply-add.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparcima\fR\fR
.ad
.sp .6
.RS 4n
Accept instructions defined for the \fBsparcima\fR version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparc4\fR\fR
.ad
.sp .6
.RS 4n
Accept instructions defined for the sparc4 version of the SPARC-V9 ISA, which are instructions from the SPARC-V9 instruction set, plus the extensions, which includes VIS 1.0, the UltraSPARC-III extensions, which includes VIS 2.0, the fused floating-point multiply-add instructions, VIS 3.0, and SPARC4 instructions.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparcace\fR\fR
.ad
.sp .6
.RS 4n
Accept instructions defined for the sparcace version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add, and SPARCACE instructions.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBsparcaceplus\fR\fR
.ad
.sp .6
.RS 4n
Accept instructions defined for the sparcaceplus version of the SPARC-V9 ISA which are instructions from the SPARC-V9 instruction set, plus the UltraSPARC extensions, including the Visual Instruction Set (VIS) version 1.0, the UltraSPARC-III extensions, including the Visual Instruction Set (VIS) version 2.0, the SPARC64 VI extensions for floating-point multiply-add, and the SPARC64 VII extensions for integer multiply-add, SPARCACE, and SPARCACEPLUS instructions.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBv9\fR\fR
.ad
.sp .6
.RS 4n
Equivalent to: \fB-m64\fR \fB-xarch\fR=\fBsparc\fR
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBv9a\fR\fR
.ad
.sp .6
.RS 4n
Equivalent to: \fB-m64\fR \fB-xarch\fR=\fBsparcvis\fR
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xarch\fR=\fBv9b\fR\fR
.ad
.sp .6
.RS 4n
Equivalent to: \fB-m64\fR \fB-xarch\fR=\fBsparcvis2\fR
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xF\fR\fR
.ad
.sp .6
.RS 4n
Generates additional information for use by the Oracle Solaris Studio performance Analyzer. If the input file does not contain any stabs (debugging directives), then the assembler will generate the default stabs needed by the Oracle Solaris Studio analyzer. Also see the \fBdbx(1)\fR Oracle Sun Studio manual page.
.RE

.SS "x86 Options"
.sp
.ne 2
.mk
.na
\fB\fB-a32\fR\fR
.ad
.sp .6
.RS 4n
Allow 32-bit addresses in 64-bit mode.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-H\fR\fR
.ad
.sp .6
.RS 4n
Generate the Hardware Capabilities section. (This is the default.)
.RE

.sp
.ne 2
.mk
.na
\fB\fB-nH\fR\fR
.ad
.sp .6
.RS 4n
Suppress the generation of the Hardware Capabilities section.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-KPIC\fR\fR
.ad
.sp .6
.RS 4n
Check for address referencing with absolute relocation and issue warning.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-xchip\fR=\fIv\fR\fR
.ad
.sp .6
.RS 4n
When there is a choice between several possible encodings, choose the one that is appropriate for the stated chip. In particular, use the appropriate no-op byte sequence to fill code alignment padding, and warn when instructions not defined for the stated chip are used.
.sp
The assembler accepts the instruction sets for the following recognized \fB-xchip\fR values:
.sp
.ne 2
.mk
.na
\fB\fBgeneric\fR\fR
.ad
.RS 15n
.rt  
generic x86 instruction set.
.RE

.sp
.ne 2
.mk
.na
\fB\fBnative\fR\fR
.ad
.RS 15n
.rt  
this host processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBcore2\fR\fR
.ad
.RS 15n
.rt  
Intel Core2 processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBnehalem\fR\fR
.ad
.RS 15n
.rt  
Intel Nehalem processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBopteron\fR\fR
.ad
.RS 15n
.rt  
AMD Opteron processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBpenryn\fR\fR
.ad
.RS 15n
.rt  
Intel Penryn processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBpentium\fR\fR
.ad
.RS 15n
.rt  
Intel Pentium architecture.
.RE

.sp
.ne 2
.mk
.na
\fB\fBpentium_pro\fR\fR
.ad
.RS 15n
.rt  
Intel Pentium Pro architecture.
.RE

.sp
.ne 2
.mk
.na
\fB\fBpentium3\fR\fR
.ad
.RS 15n
.rt  
Intel Pentium 3 style processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBpentium4\fR\fR
.ad
.RS 15n
.rt  
Intel Pentium 4 style processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBsandybridge\fR\fR
.ad
.RS 15n
.rt  
Intel Sandy Bridge processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBwestmere\fR\fR
.ad
.RS 15n
.rt  
Intel Westmere processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBamdfam10\fR\fR
.ad
.RS 15n
.rt  
AMD FAM10 processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBivybridge\fR\fR
.ad
.RS 15n
.rt  
Intel Ivy Bridge processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBhaswell\fR\fR
.ad
.RS 15n
.rt  
Intel Haswell processor.
.RE

.sp
.ne 2
.mk
.na
\fB\fBbroadwell\fR\fR
.ad
.RS 15n
.rt  
Intel Broadwell
.RE

.RE

.sp
.ne 2
.mk
.na
\fB\fB-xmodel\fR=[\fBsmall\fR | \fBmedium\fR | \fBkernel\fR]\fR
.ad
.sp .6
.RS 4n
For \fB-m64\fR only, generate \fBR_X86_64_32S\fR relocatable type for data access under \fBkernel\fR. Otherwise, generate \fBR_X86_64_32\fR under \fBsmall\fR. \fBSHN_AMD64_LCOMMON\fR and \fB\&.lbcomm\fR support added under \fBmedium\fR. \fBsmall\fR is the default.
.RE

.sp
.ne 2
.mk
.na
\fB\fB-Yd\fR,\fIpath\fR\fR
.ad
.sp .6
.RS 4n
Specify path to the version of \fBcm4defs\fR to use.
.RE

.SH ENVIRONMENT VARIABLES
.sp
.ne 2
.mk
.na
\fB\fBTMPDIR\fR\fR
.ad
.sp .6
.RS 4n
\fBas\fR normally creates temporary files in the directory \fB/tmp\fR. You may specify another directory by setting the environment variable \fBTMPDIR\fR to your chosen directory. (If \fBTMPDIR\fR is not a valid directory, then \fBas\fR will use \fB/tmp\fR).
.RE

.SH FILES
.sp
.LP
By default, \fBas\fR creates its temporary files in \fB/tmp\fR.
.SH ATTRIBUTES
.sp
.LP
See \fBattributes\fR(5) for descriptions of the following attributes:
.sp

.sp
.TS
tab() box;
cw(2.75i) |cw(2.75i) 
lw(2.75i) |lw(2.75i) 
.
ATTRIBUTE TYPEATTRIBUTE VALUE
_
Availabilitysystem/
_
Interface StabilityCommitted
.TE

.SH SEE ALSO
.sp
.LP
\fBcpp\fR(1), \fBld\fR(1), \fBm4\fR(1), \fBnm\fR(1), \fBstrip\fR(1), \fBtmpnam\fR(3C), \fBa.out\fR(4), \fBattributes\fR(5)
.SH NOTES
.sp
.LP
On SPARC platforms, the \fBcpp\fR symbol \fB__sparc\fR is set when the flag \fB-P\fR appears, as well as \fB__sparcv8\fR with the \fB-m32\fR flag, and \fB__sparcv9\fR with the \fB-m64\fR flag.
.sp
.LP
On x86/x64, the symbol \fB__i386\fR is set when the flag \fB-P\fR appears, as well as \fB__amd64\fR with the \fB-m64\fR flag.
.sp
.LP
If the \fB-m\fR (invoke the \fBm4\fR(1) macro processor) option is used, keywords for \fBm4\fR cannot be used as symbols (variables, functions, labels) in the input file since \fBm4\fR cannot determine which keywords are assembler symbols and which keywords are real \fBm4\fR macros.
.sp
.LP
Whenever possible, you should access the assembler through a compilation system interface program such as the Oracle Solaris Studio C compiler, \fBcc\fR, to ensure proper library linking. See the \fBcc(1)\fR Oracle Solaris Studio man page.